The present invention relates generally to GaAs FET devices, and more particularly to self-aligned GaAs FET devices which are unaffected by surface charge trapping/emission effects and thus are unaffected by 1/f noise sources.
In fabricating field effect transistors (FET), either GaAs or silicon is utilized as the semi-conductor material. However, GaAs is the preferred semi-conductor material because its n-channel mobility is 3-5 times faster than in silicon. Additionally, optical devices are made only in GaAs and not silicon. Accordingly, if it is desired to combine electrical and optical devices in an integrated circuit, then GaAs semi-conductor material is required.
One of the preferred fabricating techniques for FET's generally is to locate the source and drain directly adjacent to and on either side of the gate electrode. In such a design, the gate electrode may then be used as a mask for self-aligning the source and the drain relative thereto. However, if the source and the gate or the drain and the gate are actually in contact, than there will be an electrical short circuit. This short circuit problem is obviated in silicon FET devices simply by using a metaloxide semi-conductor (MOS) or an MIS structure. In the MOS structure, a layer of oxide is disposed between the gate electrode and the source and the drain regions thereby preventing the short circuit. By then applying a bias voltage to this insulated gate electrode structure, an active channel may be created below the gate in order to facilitate FET operation. However, a Schottky barrier gate cannot be fabricated with MOS or MIS structures due to the insulating layer utilized.
However, for the preferred GaAs semi-conductor material, it is not possible to invert the surface potential thereof because the Fermi level is locked at the surface. This surface Fermi level cannot be moved around with a bias voltage, thus precluding the use of MIS or MOS structures with GaAs. The lack of an ability to use MIS or MOS semiconductor structures with GaAs precludes the use of the gate/oxide self-alignment fabrication technique with GaAs.
A typical GaAs FET structure is shown in FIG. 1. An n-type doped GaAs channel 10 is shown in the figure formed on a semi-insulating GaAs substrate 11. A gate electrode 12 is disposed on a portion of the surface of the channel 10. A source region 14 of highly doped n.sup.+ material is formed in the channel 10 on one side of the gate 12, while a drain region 16 of highly doped n.sup.+ material is formed in the channel 10 on the other side of the gate 12. In order to prevent a short circuit between the source 14 and the gate 12, an open surface space 18 is disposed therebetween. Likewise, in order to prevent a short circuit between the drain region 16 and the gate 12, an open surface space 20 is disposed therebetween. The use of this type of spacing to prevent short circuits clearly obviates the ability to use the gate electrode 12 as a mask for the self-alignment of the source and the drain regions during fabrication. Please note that the source-to-gate and the gate-to-drain spacings are exaggerated in FIG. 1 to demonstrate certain adverse aspects of the standard FET structure.
The GaAs FET structure shown in FIG. 1 operates as an amplifier and/or an oscillator depending on how the device is connected and biased via its external circuitry. The general FET operating principal is that the electron current flow in the channel 10 from the source 14 to the drain 16 is modulated by the bias on the gate electrode 12 which controls the depth of a depletion region 22 formed in the channel 10 directly below the gate 12. For an n-type doped GaAs substrate, the depletion region is formed by applying a negative voltage to the gate electrode 12 to thereby repel electrons out of the depletion region 22 directly below the gate 12. A small change in the bias voltage on the electrode gate 12 changes the depth of the depletion region 22 into the n-type doped GaAs channel 10 and thereby causes a substantial change in the drain current I.sub.ds. This action is the basis for FET operation.
One of the difficulties caused by the design shown in FIG. 1 is that the surfaces spaces 18 and 20, which are required to prevent the short circuit of the device, are subject to surface charge trapping and emission of electrons. This charge trapping/emission is related to dangling bonds at the surface of the semiconductor. These dangling or unpaired bonds comprise trapping sites for electrons. The unpaired bonds present may be due to TAMM states in the native crystal lattice and due to contaminating atoms on the surface of the semiconductor. Electrons may become trapped in these trapping sites and re-emitted into the active channel, thus forming the basis for a 1/f noise source, as described below. In essence, a volume 26 in the channel 10 below the open space 18 in the GaAs n-doped substrate 10 forms a depletion region directly adjacent to the main depletion region 22 formed below the gate 12. Likewise, the volume 28 in the GaAs n-doped semiconductor substrate 10 directly below the open space 20 forms a third depletion region adjacent the main depletion region 22. The shifting occupation of the trap sites on the surfaces 18 and 20 due to the trapping and emission phenomena act to change the size of the depletion regions 26 and 28 and thereby perturb the electron flow in the active channel region 10. This perturbation caused by the trapping/emission phenomena causes fluctuations in the current in the active region of channel 10 and is thus a major source of noise. Such noise is typically referred to as 1/f noise. Such 1/f noise places specific limits on the operation of GaAs FET devices and limits their use in such applications as voltage controlled frequency).
There are presently no known designs to minimize the above-noted 1/f noise effects except through surface passivation such as through the use of SiO.sub.2 Si.sub.3 N.sub.4, Al.sub.2 O.sub.3, etc., on the exposed surfaces However, as cited by Pacel and Curtis in the 1983 IEEE MTT-S digest, pages 282-284, such passivation techniques will not obviate 1/f noise sufficently for device usage in applications such as voltage controlled oscillators.